1. Field of the Invention
The present invention relates to a method for manufacturing a heterojunction type of compound semiconductor integrated circuit and the heterojunction type of compound semiconductor integrated circuit, and, in particular, to a method for manufacturing a circuit comprising a semi-insulating substrate, a vertical heterojunction type of PNP bipolar transistor formed on the semi-insulating substrate, and a vertical heterojunction type of NPN bipolar transistor formed on the semi-insulating substrate, and the circuit.
2. Description of Background
Nowadays, high density and large integrated semiconductor circuits have been developed so that the process in the circuit is implemented at high speed. Therefore, for example, bipolar transistors have been efficiently utilized.
In a method for utilizing bipolar transistors, the precise control of a base region can be easily implemented as compared with the control of a channel length of a metal-oxide-semiconductor (MOS) transistor. Therefore, the process in the bipolar transistor can be easily implemented at high speed. However, there are drawbacks in that the separation of the bipolar transistors is difficult and the number of the processing steps for manufacturing the bipolar transistors on a substrate is large.
Therefore, an integrated injection logic (IIL) circuit has been proposed to solve the above drawbacks.
FIG. 1 is a cross sectional view of a silicon IIL circuit. FIG. 2 is an equivalent circuit of the IIL shown in FIG. 1.
As shown in FIG. 1, a silicon IIL circuit 11 comprises:
an N.sup.+ type silicon semiconductor substrate 12 with heavily doped donors; PA1 an N type silicon epitaxial grown layer 13 in which device regions are formed; PA1 a P.sup.+ type emitter diffused layer 14 formed in one of the device regions with heavily doped acceptors, an electrode E being attached on the emitter diffused layer 14; PA1 a P.sup.+ type base diffused layer 15 formed in the other device region with heavily doped acceptors, an electrode B being attached on the base diffused layer 15; PA1 a pair of N.sup.+ type diffused layers 16 (16a, 16b), electrodes C1, C2 being attached on the base diffused layer 15; and PA1 a thermal oxidation film 17 for shielding both the silicon epitaxial grown layer 13 and the base diffused layer 15. PA1 preparing an N type substrate made of a first compound semiconductor, the substrate insulating positive holes transmitted in the PNP transistor; PA1 limitedly depositing a P type second compound semiconductor on a part of the substrate, the second compound semiconductor functioning as an emitter off the PNP transistor; PA1 depositing an N type third compound semiconductor on both the second compound semiconductor and the substrate, the third compound semiconductor on the second compound semiconductor functioning as a base of the PNP transistor; PA1 strongly inverting the N type third compound semiconductor positioned on a part of the second compound semiconductor to a P.sup.+ type third compound semiconductor, the P.sup.+ type third compound semiconductor reaching the part of second compound semiconductor from the surface of the third compound semiconductor; PA1 limitedly depositing a P type fourth compound semiconductor on a part of the N type third compound semiconductor, PA1 (1) the fourth compound semiconductor being spaced from the P.sup.+ type third compound semiconductor, PA1 (2) a part of the fourth compound semiconductor being arranged just above the second compound semiconductor, and PA1 (3) the part of the fourth compound semiconductor functioning as a collector of the PNP transistor; PA1 depositing an N type fifth compound semiconductor on both the third and fourth compound semiconductors, the P.sup.+ type third compound semiconductor being covered by the fifth compound semiconductor; PA1 strongly inverting the N type fifth compound semiconductor covering the P.sup.+ type third compound semiconductor to a first P.sup.+ type fifth compound semiconductor, PA1 (1) the first P.sup.+ type fifth compound semiconductor reaching the P.sup.+ type third compound semiconductor from the surface of the fifth compound semiconductor, PA1 (2) both the P.sup.+ type third compound semiconductor and the first P.sup.+ type fifth compound semiconductor functioning as an emitter contact layer of the PNP transistor; PA1 strongly inverting the N type fifth compound semiconductor arranged on the part of the fourth compound semiconductor to a second P.sup.+ type fifth compound semiconductor, the second P.sup.+ type fifth compound semiconductor functioning as a collector contact layer of the PNP transistor; and PA1 damaging the N type fifth compound semiconductor sandwiched between the first P.sup.+ type fifth compound semiconductor and the fourth compound semiconductor, PA1 (1) the damaged fifth compound semiconductor reaching the upper portion of the third compound semiconductor, PA1 (2) atomic bonds in the damaged fifth compound semiconductor being cut off, and PA1 (3) a flat surface being formed by the N type fifth compound semiconductor, the first P.sup.+ type fifth compound semiconductor, the second P.sup.+ type fifth compound semiconductor, and the damaged fifth compound semiconductor. PA1 strongly inverting spaced portions of the N type fifth compound semiconductor on the remaining part of the fourth compound semiconductor to spaced P.sup.+ type fifth compound semiconductors, PA1 (1) the N type third compound semiconductor on the substrate functioning an emitter of an NPN transistor, PA1 (2) the remaining part of the fourth compound semiconductor functioning as a base of the NPN transistor, PA1 (3) each spaced P.sup.+ type fifth compound semiconductor insulating electrons which are transmitted from the substrate to the remaining part of the fourth compound semiconductor through the N type third compound semiconductor, and PA1 (4) spaced N type fifth compound semiconductors respectively sandwiched between the spaced P.sup.+ type fifth compound semiconductors being formed, and PA1 (5) each spaced N type fifth compound semiconductor functioning as a collector of the NPN transistor. PA1 an N type substrate made of a first compound semiconductor for mounting the PNP transistor and for insulating positive holes transmitted in the PNP transistor; PA1 a P type second compound semiconductor limitedly arranged on a part of the substrate for functioning as an emitter of the PNP transistor; PA1 an N type third compound semiconductor arranged on both the second compound semiconductor and the substrate for functioning as a base of the PNP transistor, electrons being applied from the substrate to the third compound semiconductor; PA1 a P type fourth compound semiconductor limitedly arranged on a part of the N type third compound semiconductor, PA1 (1) a part of the fourth compound semiconductor being arranged just above a first part of the second compound semiconductor, and PA1 (2) the part of the fourth compound semiconductor functioning as a collector of the PNP transistor; PA1 a P.sup.+ type fifth compound semiconductor limitedly arranged on the part of the fourth compound semiconductor for functioning as a collector contact layer of the PNP transistor; PA1 an emitter contact layer limitedly arranged on a second part of the second compound semiconductor for supplying positive holes to the second compound semiconductor, the surface of the emitter contact layer being the same height as that of the fifth compound semiconductor so as to form a flat surface; and PA1 an isolation region sandwiched between the emitter contact layer and the fifth compound semiconductor for electrically isolating the emitter contact layer from both the second P.sup.+ type fifth compound semiconductor and the fourth compound semiconductor, the surface of the isolation region being the same height as the flat surface. PA1 spaced N type sixth compound semiconductors arranged on the remaining part of the fourth compound semiconductors for respectively functioning as a collector of an NPN transistor, PA1 (1) the surface of the sixth compound semiconductors being the same height as the flat surface, PA1 (2) the remaining part of the fourth compound semiconductor functioning as a base of the NPN transistor, and PA1 (3) the third compound semiconductor just under the remaining part of the fourth compound semiconductor functioning as an emitter of the NPN transistor; and PA1 spaced P type seventh compound semiconductors respectively sandwiched between the sixth compound semiconductors for electrically isolating one sixth compound semiconductor from the other sixth compound semiconductors, the surface of the sixth compound semiconductors being the same height as the flat surface. PA1 preparing an N type substrate made of a first compound semiconductor, the substrate insulating positive holes transmitted in the PNP transistor; PA1 depositing a P type second compound semiconductor on the substrate, PA1 (1) the second compound semiconductor being provided with a plurality of openings, and PA1 (2) the second compound semiconductor functioning as an emitter of the PNP transistor; PA1 depositing an N type third compound semiconductor on the second compound semiconductor, PA1 (1) the third compound semiconductor being directly deposited on the substrate through the openings, and PA1 (2) the third compound semiconductor on the second compound semiconductor functioning as a base of the PNP transistor; PA1 strongly inverting the N type third compound semiconductor positioned on a part of the second compound semiconductor to a P.sup.+ type third compound semiconductor, the P.sup.+ type third compound semiconductor reaching the part of second compound semiconductor from the surface of the third compound semiconductor; PA1 limitedly depositing a P type fourth compound semiconductor on a part of the N type third compound semiconductor, PA1 (1) the fourth compound semiconductor being spaced from the P.sup.+ type third compound semiconductor, PA1 (2) a part of the fourth compound semiconductor being arranged just above the second compound semiconductor, PA1 (3) the part of the fourth compound semiconductor functioning as a collector of the PNP transistor, and PA1 (4) the remaining part of the fourth compound semiconductor being arranged just above the openings; PA1 depositing an N type fifth compound semiconductor on both the third and fourth compound semiconductors, the P.sup.+ type third compound semiconductor being covered by the fifth compound semiconductor; PA1 strongly inverting the N type fifth compound semiconductor covering the P.sup.+ type third compound semiconductor to a first P.sup.+ type fifth compound semiconductor, PA1 (1) the first P.sup.+ type fifth compound semiconductor reaching the P.sup.+ type third compound semiconductor from the surface of the fifth compound semiconductor, and PA1 (2) both the P.sup.+ type third compound semiconductor and the first P.sup.+ type fifth compound semiconductor functioning as an emitter contact layer of the PNP transistor; PA1 strongly inverting the N type fifth compound semiconductor arranged on the part of the fourth compound semiconductor to a second P.sup.+ type fifth compound semiconductor; PA1 damaging the N type fifth compound semiconductor sandwiched between the first P.sup.+ type fifth compound semiconductor and the fourth compound semiconductors. PA1 (1) the damaged fifth compound semiconductor reaching the upper portion of the third compound semiconductor, and PA1 (2) atomic bonds in the damaged fifth compound semiconductor being cut off; and PA1 damaging spaced portions of the second P.sup.+ type fifth compound semiconductor, PA1 (1) spaced P.sup.+ type fifth compound semiconductors being respectively formed between the damaged space portions, PA1 (2) atomic bonds in the spaced P.sup.+ type fifth compound semiconductors being cut off, PA1 (3) each spaced P.sup.+ type fifth compound semiconductor functioning as a collector contact layer of the PNP transistor, and PA1 (4) a flat surface being formed by the N type fifth compound semiconductor, the first P.sup.+ type fifth compound semiconductor, the spaced P.sup.+ type fifth compound semiconductors, the damaged fifth compound semiconductor, and the damaged space portions. PA1 an N type substrate made of a first compound semiconductor for mounting the PNP transistor and for insulating positive holes transmitted in the PNP transistor; PA1 a P type second compound semiconductor limitedly arranged on a part of the substrate for functioning as an emitter of the PNP transistor; PA1 an N type third compound semiconductor arranged on both the second compound semiconductor and the substrate for functioning as a base of the PNP transistor, electrons being applied from the substrate to the third compound semiconductor; PA1 spaced P type fourth compound semiconductors limitedly arranged just above a first part of the second compound semiconductor, each fourth compound semiconductor functioning as a collector of the PNP transistor: PA1 spaced P.sup.+ type fifth compound semiconductors arranged on the spaced P type fourth compound semiconductors for respectively functioning as a collector contact layer of the PNP transistor; PA1 collector isolation regions respectively sandwiched between the spaced P type fourth compound semiconductors and between the spaced P.sup.+ type fifth compound semiconductors for electrically isolating the fifth compound semiconductors from one another; PA1 an emitter contact layer limitedly arranged on a second part of the second compound semiconductor for supplying positive holes to the second compound semiconductor, the surface of the emitter contact layer being the same height as that of the fifth compound semiconductors so as to form a flat surface; and PA1 an emitter isolation region sandwiched between the emitter contact layer and the fourth compound semiconductor for electrically isolating the emitter contact layer from both the spaced P.sup.+ type fifth compound semiconductor and the spaced P type fourth compound semiconductor, the surface of the emitter isolation region being the same height as the flat surface. PA1 preparing a semi-insulating substrate for mounting the PNP transistor on the substrate; PA1 depositing an N type first compound semiconductor on the substrate for insulating positive holes transmitted in the PNP transistor; PA1 limitedly depositing a P type second compound semiconductor on a first part of the first compound semiconductor, the second compound semiconductor functioning as a collector of the PNP transistor; PA1 depositing an N type third compound semiconductor on both the second compound semiconductor and the first compound semiconductor, the third compound semiconductor on the second compound semiconductor functioning as a base of the PNP transistor; PA1 strongly inverting the N type third compound semiconductor positioned on a first part of the second compound semiconductor to a P.sup.+ type third compound semiconductor, the P.sup.+ type third compound semiconductor reaching the part of second compound semiconductor from the surface of the third compound semiconductor; PA1 limitedly depositing a P type fourth compound semiconductor on the N type third compound semiconductor, PA1 (1) the fourth compound semiconductor being deposited just above a second part of the second compound semiconductor, and PA1 (2) the fourth compound semiconductor functioning as an emitter of the PNP transistor; PA1 depositing an N type fifth compound semiconductor on both the third and fourth compound semiconductors, the P.sup.+ type third compound semiconductor being covered by the fifth compound semiconductor; PA1 strongly inverting the N type fifth compound semiconductor covering the P.sup.+ type third compound semiconductor to a first P.sup.+ type fifth compound semiconductor, PA1 (1) the first P.sup.+ type fifth compound semiconductor reaching the P.sup.+ type third compound semiconductor from the surface of the fifth compound semiconductor, and PA1 (2) both the P.sup.+ type third compound semiconductor and the first P.sup.+ type fifth compound semiconductor functioning as a collector contact layer of the PNP transistor; PA1 strongly inverting the N type fifth compound semiconductor arranged on the fourth compound semiconductor to a second P.sup.+ type fifth compound semiconductor, the second P.sup.+ type fifth compound semiconductor functioning as an emitter contact layer of the PNP transistor; PA1 strongly inverting the N type fifth compound semiconductor arranged just above a third part of the second compound semiconductor to an N.sup.+ type fifth compound semiconductor, the N.sup.+ type fifth compound semiconductor functioning as a base contact layer of the PNP transistor: and PA1 damaging the N type fifth compound semiconductor arranged just above the remaining part of the second compound semiconductor so as to electrically separate the first P.sup.+ type fifth compound semiconductor, the second P.sup.+ type Fifth compound semiconductor and the N.sup.+ type fifth compound semiconductor from one another, PA1 (1) the damaged fifth compound semiconductor reaching the upper portion of the third compound semiconductor, PA1 (2) atomic bonds in the damaged fifth compound semiconductor being cut off, and PA1 (3) a flat surface being formed by the N type fifth compound semiconductor, the first P.sup.+ type fifth compound semiconductor, the second P.sup.+ type fifth compound semiconductor, the N.sup.+ type fifth compound semiconductor, and the damaged fifth compound semiconductor. PA1 depositing a P type sixth compound semiconductor sandwiched between the N type third and fifth compound semiconductors arranged just above a second part of the first compound semiconductor, PA1 (1) the N type third compound semiconductor on the second part of the first compound semiconductor functioning as a collector of an NPN transistor, and PA1 (2) the sixth compound semiconductor functioning as a base of the NPN transistor; PA1 strongly inverting the N type third and fifth compound semiconductors on a third part of the first compound semiconductor to an N.sup.+ type compound semiconductor, the N.sup.+ type compound semiconductor functioning as a collector contact layer of the NPN transistor; PA1 strongly inverting the N type fifth compound semiconductor on a part of the sixth compound semiconductor to a third P.sup.+ type fifth compound semiconductor, PA1 (1) the third P.sup.+ type fifth compound semiconductor functioning as a base contact layer of the NPN transistor, and PA1 (2) the fifth compound semiconductor on the remaining part of the sixth compound semiconductor functioning as an emitter of the NPN transistor; PA1 damaging the N type fifth compound semiconductor other than the fifth compound semiconductor on the remaining part of the sixth compound semiconductor, PA1 (1) the damaged fifth compound semiconductor reaching the upper portion of the third compound semiconductor, and PA1 (2) atomic bonds in the damaged fifth compound semiconductor being cut off. PA1 a semi-insulating substrate for mounting the PNP transistor; PA1 an N type first compound semiconductor arranged on the semi-insulating substrate for insulating positive holes transmitted in the PNP transistor; PA1 a P type second compound semiconductor limitedly arranged on a first part of the first compound semiconductor for functioning as a collector of the PNP transistor; PA1 a collector contact layer limitedly arranged on a first part of the second compound semiconductor for receiving positive holes from the second compound semiconductor; PA1 an N type third compound semiconductor arranged on both the second compound semiconductor and the first compound semiconductor, the third compound semiconductor on the second compound semiconductor functioning as a base of the PNP transistor; PA1 a P type fourth compound semiconductor arranged on the N type third compound semiconductor, PA1 (1) the fourth compound semiconductor being arranged just above a second part of the second compound semiconductor, and PA1 (2) the fourth compound semiconductor functioning as an emitter of the PNP transistor; PA1 an emitter contact layer arranged on the fourth compound semiconductor for supplying the positive holes to the fourth compound semiconductor, the surface of the emitter contact layer being the same height as that of the collector contact layer so as to form a flat surface; PA1 a base contact layer arranged just above a third part of the second compound semiconductor for applying a negative voltage to the third compound semiconductor. The surface of the base contact layer being the same height as the flat surface; and PA1 isolation regions arranged on the third compound semiconductor for electrically isolating the emitter contact layer, the base contact layer and the collector contact layer from one another, each surface of the isolation regions being the same height as the flat surface. PA1 a P type sixth compound semiconductor arranged on the N type third compound semiconductor, PA1 (1) the fifth compound semiconductor being interposed between the fourth compound semiconductor and the second part of the first compound semiconductor, PA1 (2) the fifth compound semiconductor functioning as a base of an NPN transistor, and PA1 (3) the third compound semiconductor on the second part of the first compound semiconductor functioning as a collector of the NPN transistor; PA1 an NPN collector contact layer arranged on the third compound semiconductor for receiving electrons from the third compound semiconductor, PA1 (1) the NPN collector contact layer being limitedly arranged just above a third part of the first compound semiconductor, and PA1 (2) the surface of the NPN collector contact layer being the same height as the flat surface; an NPN base contact layer limitedly arranged on a part of the fifth compound semiconductor for applying a positive voltage to the sixth compound semiconductor, the surface of the NPN base contact layer being the same height as the flat surface; PA1 an N type sixth compound semiconductor limitedly arranged on the remaining part of the fifth compound semiconductor for functioning as an emitter of the NPN transistor the surface of the sixth compound semiconductor being the same height as the flat surface; and PA1 an NPN isolation region sandwiched between the NPN collector contact layer and the fourth compound semiconductor for electrically isolating the NPN collector contact layer from both the sixth compound semiconductor and the NPN base contact layer, the surface of the NPN isolation region being the same height as the flat surface.
A horizontal PNP bipolar transistor 18 is fabricated by the silicon epitaxial grown layer 13 (base of transistor 18), the emitter diffused layer 14 (emitter of transistor 18), and the base diffused layer 15 (collector of transistor 18). In addition, a vertical NPN bipolar transistor 19 is fabricated by the silicon epitaxial grown layer 13 (emitter of transistor 19), the base diffused layer 15 (base of transistor 19), and the diffused layers 16 (collector of transistor 19).
In the above configuration, the operation in the silicon IIL circuit 11 is described with reference to FIG. 2.
The electrode E is set at a high positive electric potential, and the silicon semiconductor substrate 12 is set at a negative electric potential. In this condition, when an input terminal connected with the electrode B is set at a low electric potential, positive holes are injected from the electrode E to the electrode B through the horizontal PNP bipolar transistor 18. That is, the positive holes are transmitted from the emitter diffused layer 14 to the base diffused layer 15 through the silicon epitaxial grown layer 13. Also, the vertical NPN bipolar transistor 19 is turned off so that the electric potential of output terminals connected with the electrodes C1, C2 are kept at a high electric potential.
Accordingly, when the input terminal is set at the low electric potential, the output terminals are kept at the high electric potential.
On the other hand, when the input terminal is set at a high electric potential, positive holes are injected from the electrode E to the silicon epitaxial grown layer 13 through both the horizontal PNP bipolar transistor 18 and the vertical NPN bipolar transistor 19. Therefore, the vertical NPN bipolar transistor 19 is turned on so that the electric potential of the output terminals is changed at a low electric potential.
Accordingly, when the input terminal is set at the high electric potential, the output terminals are changed at the low electric potential.
Therefore, the silicon IIL circuit 11 functions as a NOT circuit with multiple output terminals. In addition, the electrode E is operated as an injector.
In general, the number of the output terminals must agree with the number of the diffused layers 16. However, even though a large number of output terminals are required, the diffused layer 16 can be easily increased because the diffused layers 16 are fabricated in the base diffused layer 15 in parallel.
In addition, the manufacturing process in the silicon IIL circuit 11 is simplified. A first reason is that both the horizontal PNP bipolar transistor 18 and the vertical NPN bipolar transistor 19 are fabricated in the silicon epitaxial grown layer 13. A second reason is that the base of the horizontal PNP bipolar transistor 18 shares the silicon epitaxial grown layer 13 with the emitter of the vertical NPN bipolar transistor 19. A third reason is that the collector of the horizontal PNP bipolar transistor 18 shares the base diffused layer 15 with the base of the vertical NPN bipolar transistor 19.
Therefore, a large integrated silicon IIL circuit 11 can be easily manufactured.
However, frequency characteristics deteriorate in the silicon IIL circuit 11 because the vertical NPN bipolar transistor 19 is operated in a reverse connection region. In addition, propagation delay time is prolonged because minority carriers (positive holes) are stored in the silicon epitaxial grown layer 13.
Next, another conventional silicon IIL circuit in which the frequency characteristics and the propagation delay time are improved is described with reference to FIG. 3.
As shown in FIG. 3, a silicon IIL circuit 21 is provided with an emitter diffused layer 22 prolonged directly under the base diffused layer 15 in place of the emitter diffused layer 14 as compared with the silicon IIL circuit 11. That is, a vertical PNP bipolar transistor 23 is fabricated in the silicon IIL circuit 21.
Therefore, the positive holes stored in the silicon epitaxial grown layer 13 are decreased because the surface area transmitting the positive holes from the emitter diffused layer 22 is increased. Therefore, the propagation delay time is shortened so that the lifetime of the positive holes is substantially shortened.
Accordingly, the frequency characteristics are improved so that a current amplification factor h.sub.fe in the PNP transistor is improved.
In addition, because the vertical PNP bipolar transistor 23 is fabricated in a vertical direction against the substrate 12, the emitter diffused layer 22 can be easily formed by controlling its diffused length regardless of whether the base thickness in the PNP transistor 23 is required to be uniform and narrow.
As a result, as shown in FIG. 4, a direct current transfer ratio .alpha. at grounded base is largely improved in the vertical PNP bipolar transistor 23. In addition, the characteristics in the relation between the direct current transfer ratio .alpha. and a collector current Ic are improved. Here, the current amplification factor h.sub.fe is equal to .alpha./(1-.alpha.) by utilizing the direct current transfer ratio .alpha..
On the other hand, in cases where a heterojunction type of bipolar transistor is made of compound semiconductors, both the emitter capacitance and the base resistance can be decreased while the current amplification factor h.sub.fe is kept to a high value. Therefore, the heterojunction type of bipolar transistor made of compound semiconductors can be operated at high speed as compared with the heterojunction type of bipolar transistor made of silicon materials.
Recently, manufacturing techniques such as a device isolation technique, an ion implanting technique, an ion implant and isolation technique, a grading technique utilized in heterojunction interfaces (graded impurity profile technique), a self aligning technique, a miniaturing technique, and a high quality epitaxial technique has been advanced to develop the heterojunction type of bipolar transistor made of compound semiconductors. As a result, the heterojunction type of bipolar transistor is operated to generate oscillating signals at a frequency more than 100 GHz. Moreover, the operation at an oscillating frequency more than 300 GHz will be possible by miniaturing element devices in the not too distant future.
Moreover, a plurality of devices made of the compound semiconductors such as a PNP transistor, an IIL circuit, a resistor, and a capacitor are fabricated on a substrate. In this case, the compound semiconductors such as GaAs and InP have been utilized.
Therefore, for example, both the current amplification factor h.sub.fe and the propagation delay time can be further improved in the IIL circuit with a vertical PNP transistor which is made of the compound semiconductor.
However, in cases where the configuration of the IIL circuit made of the compound semiconductor is the same as that of the silicon IIL circuit 21 shown in FIG. 3, the characteristics obtained in the silicon IIL circuit 21 cannot be obtained in the IIL circuit made of the compound semiconductor. For example, the current amplification factor h.sub.fe is largely decreased as the collector current 21 is decreased. The reason is as follows.
As shown in FIG. 3, a horizontal PNP transistor 24 is parasitically fabricated by the silicon epitaxial grown layer 13, the base diffused layer 15, and the vertical portion of the emitter diffused layer 22 in the silicon IIL circuit 21. The horizontal PNP transistor 24 does not function as a heterostructure type of bipolar transistor but functions as a diffused type of bipolar transistor because the horizontal PNP transistor 24 is arranged at the surface of the silicon IIL circuit 21.
Therefore, in cases where the collector current Ic is low, direct current characteristics largely deteriorate in the silicon IIL circuit made of the compound semiconductors.
In addition, the current amplification factor h.sub.fe is decreased and fluctuates because the base thickness of the horizontal PNP transistor 24 is not determined by the width of the silicon epitaxial grown layer 13 between the base diffused layer 15 and the vertical portion of the emitter diffused layer 22 but determined by the diffusion of both the base diffused layer 15 and the vertical portion of the emitter diffused layer 22.
Moreover, alternating current characteristics deteriorates because the horizontal PNP transistor 24 does not function as a heterostructure type of bipolar transistor. For example, the frequency of oscillating signals obtained in the silicon IIL circuit made of the compound semiconductors is a several MHz at the most.
Furthermore, in cases where a plurality of devices made of the compound semiconductors such as a heterojunction type of bipolar transistor are fabricated on a substrate, the devices are formed at a mesa structure to increase an active region and decrease a saturation region so that the current amplification factor h.sub.fe is improved. However, in this case, a large number of differences in level are generated in the devices. Therefore, hard-wires connecting the devices are easily cut off at different portions in level. As a result, the devices cannot be miniaturized so that a large scaled integrated circuit cannot be manufactured in the heterojunction type of compound semiconductor.